Silicon photonics moves forward with demand from Facebook and innovations by Aurrion and STMicro
Julie Kunstler, Principal Analyst, Components
It appears that silicon photonics is defeating its skeptics. We believe that Facebook is testing non-standard silicon photonics–based 100G solutions today and that wider-scale usage could happen as early as next year.
OFC’s press/analyst luncheon on Tuesday focused on a realistic assessment of silicon photonics for the data center. The panel was led by Daryl Inniss, Ovum’s Components Practice Leader. Other participants included:
Yuval Bachar, hardware network engineer for Facebook
Greg Fish, CTO, Aurrion
Flavio Benetti, group VP and GM, Mixed Processes Division, STMicroelectronics.
Why the optimism? Two major barriers to silicon photonics are being overcome – cost and sufficient development dollars.
We highlight two vendors who are helping to break down these barriers: Aurrion and STMicro. Both are uniting the worlds of photonics and silicon-based microsystems, enabling silicon photonics to benefit from well-established, low-cost manufacturing processes. Their respective starting points, though, are quite different. Aurrion is a start-up company headquartered in Santa Barbara, California, while STMicro is a large publicly traded semiconductor manufacturer headquartered in Geneva, Switzerland.
According to Greg Fish, Aurrion was established to scale photonics, with the hope that bringing down the costs would drive adoption. In agreement, STMicro’s Flavio Benetti stated that silicon photonics will succeed when its manufacturing processes mirror those of the IC world.
Yuval Bachar commented that 40G is not sufficient for Facebook anymore – the giant social networking service needs 100G at reasonable prices. According to Bachar, silicon photonics will enable 100G to approach $1 for 1G, making it more attractive to the market.
The major obstacles to silicon photonics are being tackled, although more slowly than early market optimists had hoped.
JDSU 400G discrete multi-tone (DMT) modulation demonstration targets 10km duplex single-mode fiber
Daryl Inniss, Practice Leader, Components
JDSU is demonstrating an attractive new 400G solution that the company says is one of its highlights for the show. This is risky given the long time it can take to finalize a product. But high risk often brings high reward, and JDSU’s venture seems a good one in this instance.
Single carrier is the holy-grail for 400G due to the high laser cost. Sixteen lasers would be needed using today’s technology of 25G per laser. New modulation formats such as pulse-amplitude modulation (PAM) are being introduced, but the most popular one for the 400G application (PAM4) requires eight lasers. The JDSU demonstration uses four lasers and furthermore uses a modulation format that can help get the market to a single carrier.
Discrete multi-tone (DMT) technology is not new; it is used to separate signals in digital subscriber line (DSL). Fujitsu Optical Components is another DMT proponent for 400G.
JDSU’s approach is risky because the required integrated circuit needs leading-edge fabrication technology, 14nm complementary metal oxide semiconductor (CMOS), to meet the power requirements of the module. The lead time for such a chip can be lengthy. It’s not that far away, though; at the show, customers and designers can assess the technology through the demonstration, which is based on an evaluation board and chips from partner suppliers.
JDSU is well positioned to reap rewards from DMT, as increasing electronics complexity and reducing optics is the path to lower-cost high-bandwidth links.
System vendors hawking new coherent capabilities at OFC
Ron Kline, Principal Analyst, Intelligent Networks
This year’s OFC conference brought several new announcements on digital signal processing (DSP) capabilities from both system vendors and component vendors.
On the systems side, Infinera unveiled a pair of new photonic integrated circuits (PICs), which will ultimately drive its yet-unannounced metro aggregation platform. The company, which pioneered large-scale photonic integration, is introducing the ePIC-500 and oPIC-100. The PICs are part of Infinera’s “sliceable photonics” strategy. In an Infinera press release, Telefonica announced it was testing the two new PICs.
The ePIC-500 will allow 100G coherent wavelengths to be routed in different directions (sliced), as opposed to all being transported on a single 500G super-channel. The new oPIC-100 supports a single 100G channel, thereby introducing a product to receive the slices. The oPIC-100 can also be positioned at both ends of the link, but the key feature is that Infinera needed a solution to receive slices and send slices to the 500G parent. These two PICs will allow the company to adapt its PIC technology for use in the metro aggregation market.
Ciena also announced the next evolution to its WaveLogic 3 ASIC family, introducing two new chipsets. The first one, WaveLogic 3 Extreme, supports 16QAM and also a new 8D-2QAM modulation format for submarine transmission. Ciena says the Extreme provides a 40% improvement in capacity and 20% improvement in reach versus existing WaveLogic 3 chips. The second chipset, WaveLogic 3 Nano, is designed specifically for metro applications and provides a 70% reduction in power versus standard WaveLogic 3 chips. At the same time the company introduced a ROADM-less broadcast and select architecture (Flex Coherent) based on the WaveLogic 3 Nano ASIC. The architecture uses the tunable receiver capabilities in the new WaveLogic 3 Nano to select drop channels. This eliminates the need for a ROADM, thereby improving the cost efficiency of metro deployments but also somewhat lowering flexibility.
On the merchant side, both Acacia and ClariPhy made significant announcements this week:
Acacia announced the AC-400, a 5x7 flex-rate coherent 400G transceiver module. The AC-400 is powered by a dual-core ASIC supporting two optical channels and up to 400Gbps capacity, which can include a clear channel, single 400Gbps traffic flow optimized for IP packet transport. (For more analysis on the Acacia announcement, see the write-up by Daryl Inniss in “OFC 2015 Highlights: Day Two.”)
ClariPhy announced a reference design for integration of its Lightspeed 2 chip with a CFP2 slot, allowing a single board design and supporting a range of CFP2 modules. CFP2 will enable system vendors to significantly increase densities and reduce system cost per bit transmitted.
While 100G deployments are now commonplace, vendors continue to push the boundaries with new ASIC capabilities that extend the capacity reach and reduce the cost of coherent technology.