At its analyst day on December 10, 2018, Intel introduced its new 3D packaging technology, Foveros, for heterogeneous system integration. Foveros enables logic-on-logic packaging, and is designed to maximize multifunction integration. Logic, memory, radio, sensor, and photonic discrete functions may be integrated depending on the application requirements. Foveros is intended to maximize Intel's ability to meet many processing application needs with common integrated circuit (IC) building blocks.
3D packaging technology will enable combinations of processing chiplets to match applications
The network communications and processing worlds are coming together as never before. 5G mobile networks will require edge compute, radio access, and optical transmission to come together. The new 5G edge nodes will be under space and power constraints. Expensive site costs are to be avoided. Integration will be essential for competitive advantage.
Intel is targeting multiple processor application segments, from data center server CPUs and GPUs to desktop and mobile CPUs. Each application space has differing performance, power, and cost requirements, best solved by an optimized lineup of transistors and memory.
The foundational concept behind Foveros is the ability to match the optimal "chiplets" – functions with the application at hand – in an integrated logic-on-logic 3D package. Intel is not stopping at integrated logic and memory, but will also include photonics.
Execution and yield will ultimately tell the story with Foveros. Foveros, of Greek language origin, has multiple meanings, two of which Intel will strive to avoid: "dreadful" and "horrifying." Intel has on-wafer testing procedures to identify processor defects prior to integration for cost savings. Intel asserts that it has cracked the thermal dissipation challenges associated with earlier 3D packaging attempts. If all goes well, then, Foveros will be awesome, terrifying the competition.
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Ian Redpath, Practice Leader, Components, Transport and Routing